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? semiconductor components industries, llc, 2012 january, 2012 ? rev. 0 1 publication order number: NB3N200S/d NB3N200S 3.3 v differential multipoint low voltage m-lvds driver receiver description the nb3n200 is a pure 3.3 v supply differential multipoint low voltage (m ? lvds) line driver and receiver. NB3N200S is tia/eia ? 899 compliant. NB3N200S offers the type 1 receiver threshold at 0.0 v. these devices has a type ? 1 receiver that detect the bus state with as little as 50 mv of differential input voltage over a common ? mode voltage range of ? 1 v to 3.4 v. the type ? 1 receivers have near zero thresholds ( 50 mv) and exhibit 25 mv of differential input voltage hysteresis to prevent output oscillations with slowly changing signals or loss of input. NB3N200S supports simplex bus configurations. features ? low ? voltage differential 30 to 55 line drivers and receivers for signaling rates up to 200 mbps ? type ? 1 receivers incorporate 25 mv of hysteresis ? meets or exceeds the m ? lvds standard tia/eia ? 899 for multipoint data interchange ? controlled driver output voltage transition times for improved signal quality ? ? 1 v to 3.4 v common ? mode voltage range allows data transfer with up to 2 v of ground noise ? bus pins high impedance when disabled or v cc 1.5 v ? m ? lvds bus power up/down glitch free ? operating range: v cc = 3.3 10% v( 3.0 to 3.6 v) ? operation from ?40 c to 85 c. ? pb ? free soic 8 package ? these are pb ? free devices applications ? low ? power high ? speed short ? reach alternative to tia/eia ? 485 ? backplane or cabled multipoint data and clock transmission ? cellular base stations ? central ? office switches ? network switches and routers figure 1. logic diagrams marking diagram http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet. ordering information soic ? 8 d suffix case 751 1 8 nb20x ayww 1 8 nb20x = specific device code x = 0, 2, 4, 5 a = assembly location y = year ww = work week g or = pb ? free package
NB3N200S http://onsemi.com 2 b gnd v cc de a re d r 1 2 3 4 8 7 6 5 figure 2. pinout diagrams (top view) NB3N200S soic ? 8 table 1. pin description soic ? 8 number name i/o type open default description 1 r lvcmos output receiver output pin 2 re lvcmos input high receiver enable input pin (low = active, high = high z output) 3 de lvcmos input low driver enable input pin (low = high z output, high = active) 4 d lvcmos input driver output pin 5 gnd ground supply pin. pin must be externally connected to power supply to guarantee proper operation. 6 a m ? lvds input / output transceiver invert input / output pin 7 b m ? lvds input / output transceiver true input / output pin 8 vcc power supply pin. pin must be externally connected to power supply to guarantee proper operation. table 2. device function table type 1 receiver (nb3n200) inputs output v id = v a ? v b re r v id 50 mv l h ? 50 mv < v id < 50 mv l ? v id ? 50 mv l l x h z x open z open l ? driver input enable output d de a / y b / z l h l h h h h l open h l h x open z z x l z z h = high, l = low, z = high impedance, x = don?t care, ? = indeterminate
NB3N200S http://onsemi.com 3 table 3. attributes (note 1) characteristics value internal input pullup resistor 50 k internal input pulldown resistor 50 k esd protection human body model (jedec standard 22, method a114 ? a) a, b, y, z all pins 6 kv 2 kv machine model all pins 200 v charged ?device model (jedec standard 22, method c101) all pins 1500 v moisture sensitivity, indefinite time out of drypack (note 1) level 1 flammability rating oxygen index ul ? 94 v ? 0 @ 0.125 in 28 to 34 transistor count 917 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. table 4. maximum ratings (note 2) symbol parameter condition 1 condition 2 rating unit v cc supply voltage ? 0.5 v cc 4.0 v v in input voltage d, de, re ? 0.5 v in 4.0 v a, b (200, 204) ? 1.8 v in 4.0 a, b (202, 205) ? 4.0 v in 6.0 i out output voltage r y, z, a, b ? 0.3 i out 4.0 ? 1.8 i out 4.0 v t a operating temperature range, industrial ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm soic ? 8 190 130 c/w c/w jc thermal resistance (junction ? to ? case) (note 3) soic ? 8 41 to 44 c/w t sol wave solder 265 c p d power dissipation (continuous) soic ? 8 t a = 25 c 25 c < t a < 85 c t a = 85 c 725 5.8 377 mw mw/ c mw stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 2. maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simu ltaneously. if stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. 3. jedec standard multilayer board ? 2s2p (2 signal, 2 power). table 5. dc characteristics vcc = 3.3 10% v( 3.0 to 3.6 v), gnd = 0 v, t a = ? 40 c to +85 c (see notes 4, 5) symbol characteristic min typ max unit icc power supply current receiver disabled driver enabled re and de at v cc , r l = 50 , all others open driver and receiver disabled re at vcc, de at 0 v, r l = no load, all others open driver and receiver enabled re at 0 v, de at v cc , r l = 50 , all others open receiver enabled driver disabled re at 0 v, de at 0 v, r l = 50 , all others open 13 1 16 22 4 24 13 ma v ih input high voltage 2 v cc v v il input low voltage gnd 0.8 v vbus voltage at any bus terminal va, vb, vy or vz ? 1.4 3.8 v |vid| magnitude of differential input voltage 0.05 v cc driver
NB3N200S http://onsemi.com 4 table 5. dc characteristics vcc = 3.3 10% v( 3.0 to 3.6 v), gnd = 0 v, t a = ? 40 c to +85 c (see notes 4, 5) symbol unit max typ min characteristic driver |v ab | / |v yz | differential output voltage magnitude (see figure 4) 480 650 mv |v ab | / |v yz | change in differential output voltage magnitude between logic states (see figure 4) ? 50 50 mv v os(ss) steady state common mode output voltage (see figure 5) 0.8 1.2 v v os(ss) change in steady state common mode output voltage between logic states (see figure 5) ? 50 50 mv v os(pp) peak ? to ? peak common ? mode output voltage (see figure 5) 150 mv v yoc / v aoc maximum steady ? state open ? circuit output voltage (see figure 9) 0 2.4 v v zoc / v boc maximum steady ? state open ? circuit output voltage (see figure 9) 0 2.4 v v p(h) voltage overshoot, low ? to ? high level output (see figure 7) 1.2 v ss v v p(l) voltage overshoot, high ? to ? low level output (see figure 7) ? 0.2 v ss v i ih high ? level input current (d, de) v ih = 2 v 0 10 ua i il low ? level input current (d, de) v il = 0.8 v 0 10 ua ji os j differential short ? circuit output current magnitude (see figure 6) 24 ma i oz high ? impedance state output current (driver only) ? 1.4 v (vy or vz) 3.8 v, other output at 1.2 v ? 15 10 ua i o(off) power ? off output current (0 v v cc 1.5 v) ? 1.4 v (vy or vz) 3.8 v, other output at 1.2 v ? 10 10 ua c y / c z output capacitance vi = 0.4 sin(30e 6 t ) + 0.5 v, other outputs at 1.2 v using hp4194a impedance analyzer (or equivalent) 3 pf c yz differential output capacitance v ab = 0.4 sin(30e 6 t) v, other outputs at 1.2 v using hp4194a impedance analyzer (or equivalent) 2.5 pf c y/z output capacitance balance, (c y /c z ) 99 101 % receiver v it+ positive ? going differential input voltage threshold (see figure 11 & tables 8 and no tag) type 1 type 2 50 150 mv v it ? negative ? going differential input voltage threshold (see figure 11 & tables 8 and no tag) type 1 type 2 ? 50 50 mv v hys differential input voltage hysteresis (see figure 11 and table 2) type 1 type 2 25 0 mv voh high ? level output voltage (ioh = ?8 ma 2.4 v vol low ? level output voltage (iol = 8 ma) 0.4 v i ih re high-le vel input current (vih = 2 v) ? 10 0 a i il re low-le vel input current (vil = 0.8 v) ? 10 0 a i oz high ? impedance state output current (vo = 0 v of 3.6 v) ? 10 15 a c a / c b input capacitance vi = 0.4 sin(30e 6 t) + 0.5 v, other outputs at 1.2 v using hp4194a impedance analyzer (or equivalent) 3 pf c ab differential input capacitance v ab = 0.4 sin(30e 6 t) v, other outputs at 1.2 v using hp4194a impedance analyzer (or equivalent) 2.5 pf c a/b input capacitance balance, (c a /c b ) 99 101 %
NB3N200S http://onsemi.com 5 table 5. dc characteristics vcc = 3.3 10% v( 3.0 to 3.6 v), gnd = 0 v, t a = ? 40 c to +85 c (see notes 4, 5) symbol characteristic min typ (note 5) max unit bus input and output i a input current receiver or transceiver with driver disabled v a = 3.8 v, v b = 1.2 v v a = 0.0 v or 2.4 v, v b = 1.2 v v a = ? 1.4 v, v b = 1.2 v 0 ? 20 ? 32 32 20 0 ua i b input current receiver or transceiver with driver disabled v b = 3.8 v, v a = 1.2 v v b = 0.0 v or 2.4 v, v a = 1.2 v v b = ? 1.4 v, v a = 1.2 v 0 ? 20 ? 32 32 20 0 ua i ab differential input current receiver or transceiver with driver disabled (i a ? i b ) v a = v b , ? 1.4 v a 3.8 v ? 4 4 ua i a(off) input current receiver or transceiver power off 0v v cc 1.5 and: v a = 3.8 v, v b = 1.2 v v a = 0.0 v or 2.4 v, v b = 1.2 v v a = ? 1.4 v, v b = 1.2 v 0 ? 20 ? 32 32 20 0 ua i b(off) input current receiver or transceiver power off 0v v cc 1.5 and: v b = 3.8 v, v a = 1.2 v v b = 0.0 v or 2.4 v, v a = 1.2 v v b = ? 1.4 v, v a = 1.2 v 0 ? 20 ? 32 32 20 0 ua i ab(off) receiver input or transceiver input/output power off differential input current; (i a ? i b ) v a = v b , 0 v cc 1.5 v, ? 1.4 v a 3.8 v ? 4 4 ua c a transceiver input capacitance with driver disabled v a = 0.4 sin(30e 6 t) + 0.5 v using hp4194a impedance analyzer (or equivalent); v b = 1.2 v 5 pf c b transceiver input capacitance with driver disabled v b = 0.4 sin(30e 6 t) + 0.5 v using hp4194a impedance analyzer (or equivalent); v a = 1.2 v 5 pf c ab transceiver differential input capacitance with driver disabled v a = 0.4 sin(30e 6 t) + 0.5 v using hp4194a impedance analyzer (or equivalent); v b = 1.2 v 3.0 pf c a/b transceiver input capacitance balance with driver disabled, (c a /c b ) 99 101 % note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. see figure 3. dc measurements reference. 5. typ value at 25 c and 3.3 vcc supply voltage. table 6. driver ac characteristics vcc = 3.3 10% v( 3.0 to 3.6 v), gnd = 0 v, t a = ? 40 c to +85 c (note 6) symbol characteristic min typ max unit t plh / t phl propagation delay (see figure 7) 1.0 2.4 ns t phz / t plz disable time high or low state to high impedance (see figure 8) 7 ns t pzh / t pzl enable time high impedance to high or low state (see figure 8) 7 ns t sk(p) pulse skew (|t plh ? t phl |) (see figure 7) 0 150 ps t sk(pp) device to device skew similar path and conditions (see figure 7) 0.9 ns t jit(per) period jitter rms, 100 mhz (source tr/tf 0.5 ns, 10 and 90 % points, 30k samples. source jitter de ? embedded from output values ) (see figure 10) 3 ps t jit(pp) peak ? to ? peak jitter, 200 mbps 2 15 ? 1 prbs (source tr/tf 0.5 ns, 10 and 90% points, 100k samples. source jitter de ? embedded from output values) (see figure 10) 150 ps tr / tf differential output rise and fall times (see figure 7) 1 1.6 ns note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. typ value at 25 c and 3.3 v cc supply voltage.
NB3N200S http://onsemi.com 6 table 7. receiver ac characteristics vcc = 3.3 10% v( 3.0 to 3.6 v), gnd = 0 v, t a = ? 40 c to +85 c (note 7) symbol characteristic min typ max unit t plh / t phl propagation delay (see figure 12) 2 4 6 ns t phz / t plz disable time high or low state to high impedance (see figure 13) 10 ns t pzh / t pzl enable time high impedance to high or low state (see figure 13) 15 ns t sk(p) pulse skew (|t plh ? t phl |) (see figure 12) c l = 5 pf type 1 type 2 100 300 300 500 ps t sk(pp) device to device skew similar path and conditions (see figure 12) c l = 5 pf 1 ns t jit(per) period jitter rms, 100 mhz (source: vid = 200 mv pp for 201 and 203, vid = 400 mv pp for 206 and 207, v cm =1 v, tr/tf 0.5 ns, 10 and 90 % points, 30k samples. source jitter de ? embedded from output values ) (see figure 14) 4 7 ps t jit(pp) peak ? to ? peak jitter, 200 mbps 2 15 ? 1 prbs (source tr/tf 0.5 ns, 10% and 90% points, 100k samples. source jitter de ? embedded from output values) (see figure 14) type 1 type 2 300 450 700 800 ps tr / tf differential output rise and fall times (see figure 12) c l = 15 pf 1 2.3 ns 7. typ value at 25 c and 3.3 vcc supply voltage. . figure 3. driver voltage and current definitions a. all resistors are 1% tolerance. figure 4. differential output voltage test circuit
NB3N200S http://onsemi.com 7 a. all input pulses are supplied by a generator having the following characteristics: t r or t f 1 ns, pulse frequency = 500 khz, duty cycle = 50 5%. b. c1, c2 and c3 include instrumentation and fixture capacitance within 2 cm of the d.u.t. and are 20% tolerance. c. r1 and r2 are metal film, surface mount, 1% tolerance, and located within 2 cm of the d.u.t. d. the measurement of v os(pp) is made on test equipment with a ?3 db bandwidth of at least 1 ghz. figure 5. test circuit and definitions for the driver common ? mode output voltage figure 6. driver short ? circuit test circuit a. all input pulses are supplied by a generator having the following characteristics: t r or t f 1 ns, frequency = 500 khz, duty cycle = 50 5%. b. c1, c2, and c3 include instrumentation and fixture capacitance within 2 cm of the d.u.t. and are 20%. c. r1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the d.u.t. d. the measurement is made on test equipment with a ? 3 db bandwidth of at least 1 ghz. figure 7. driver test circuit, timing, and voltage definitions for the differential output signal
NB3N200S http://onsemi.com 8 a. all input pulses are supplied by a generator having the following characteristics: t r or t f 1 ns, frequency = 500 khz, duty cycle = 50 5%. b. c1, c2, c3, and c4 includes instrumentation and fixture capacitance within 2 cm of the d.u.t. and are 20%. c. r1 and r2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the d.u.t. d. the measurement is made on test equipment with a ? 3 db bandwidth of at least 1 ghz. figure 8. driver enable and disable time circuit and definitions figure 9. maximum steady state output voltage
NB3N200S http://onsemi.com 9 a. all input pulses are supplied by an agilent 8304a stimulus system. b. the measurement is made on a tek tds6604 running tdsjit3 application software c. period jitter is measured using a 100 mhz 50 1% duty cycle clock input. d. peak ? to ? peak jitter is measured using a 200 mbps 2 15 ? 1 prbs input. figure 10. driver jitter measurement waveforms figure 11. receiver voltage and current definitions
NB3N200S http://onsemi.com 10 a. all input pulses are supplied by a generator having the following characteristics: t r or t f 1 ns, frequency = 50 mhz, duty cycle = 50 5%. c l is a combination of a 20% ? tolerance, low ? loss ceramic, surface ? mount capacitor and fixture capacitance within 2 cm of the d.u.t. b. the measurement is made on test equipment with a ?3 db bandwidth of at least 1 ghz. figure 12. receiver timing test circuit and waveforms
NB3N200S http://onsemi.com 11 a. all input pulses are supplied by a generator having the following characteristics: t r or t f 1 ns, frequency = 500 khz, duty cycle = 50 5%. b. r l is 1% tolerance, metal film, surface mount, and located within 2 cm of the d.u.t. c. c l is the instrumentation and fixture capacitance within 2 cm of the dut and 20%. figure 13. receiver enable/disable time test circuit and waveforms
NB3N200S http://onsemi.com 12 a. all input pulses are supplied by an agilent 8304a stimulus system. b. the measurement is made on a tek tds6604 running tdsjit3 application software c. period jitter is measured using a 100 mhz 50 1% duty cycle clock input. d. peak ? to ? peak jitter is measured using a 200 mbps 2 15 ? 1 prbs input. figure 14. receiver jitter measurement waveforms table 8. type ? 1 receiver input threshold test voltages applied voltages resulting differential input voltage resulting common ? mode input voltage receiver output via vib vid vic 2.400 0.000 2.400 1.200 h 0.000 2.400 ?2.400 1.200 l 3.800 3.750 0.050 3.775 h 3.750 3.800 ?0.050 3.775 l ?1.350 ?1.400 0.050 ?1.375 h ?1.400 ?1.350 ?0.050 ?1.375 l h = high level, l = low level, output state assumes receiver is enabled (re = l)
NB3N200S http://onsemi.com 13 figure 15. equivalent input and output schematic diagrams application information receiver input threshold (failsafe) the mlvd standard defines a type 1 and type 2 receiver. type 1 receivers include no provisions for failsafe and have their differential input voltage thresholds near zero volts. type 2 receivers have their differential input voltage thresholds offset from zero volts to detect the absence of a voltage difference. the impact to receiver output by the offset input can be seen in table 9 and figure 16. table 9. receiver input voltage threshold requirements receiver type output low output high type 1 ?2.4 v vid ?0.05 v 0.05 v vid 2.4 v
NB3N200S http://onsemi.com 14 figure 16. receiver differential input voltage showing transition regions by type live insertion/glitch ? free power up/down the nb3n200 family of products provides a glitch ? free power up/down feature that prevents the m ? lvds outputs of the device from turning on during a power up or power down event. this is especially important in live insertion applications, when a device is physically connected to an m ? lvds multipoint bus and v cc is ramping. while the m ? lvds interface for these devices is glitch free on power up/down, the receiver output structure is not. figure 17 shows the performance of the receiver output pin, r (channel 2), as v cc (channel 1) is ramped. the glitch on the r pin is independent of the re voltage. any complications or issues from this glitch are easily resolved in power sequencing or system requirements that suspend operation until v cc has reached a steady state value.
NB3N200S http://onsemi.com 15 figure 17. m ? lvds receiver output: vcc (channel 1), r pin (channel 2) simplex theory configurations: data flow is unidirectional and point ? to ? point from one driver to one receiver. NB3N200Sdg, nb3n202sdg, nb3n204sdg, and nb3n205sdg devices provide a high signal current allowing long drive runs and high noise immunity. single terminated interconnects yield high amplitude levels. parallel terminated interconnects yield typical mlvds amplitude levels and minimizes reflections. see figures 18 and 19. a NB3N200Sdg, nb3n202sdg, nb3n204sdg, and nb3n205sdg can be used as the driver or as a receiver. figure 18. point ? to ? point simplex single termination figure 19. parallel ? terminated simplex simplex multidrop theory configurations : data flow is unidirectional from one driver with one or more receivers and multiple boards are required. single terminated interconnects yield high amplitude levels. parallel terminated interconnects yield typical mlvds amplitude levels and minimizes reflections. on the evaluation test board, headers p1, p2, and p3 may be used as need to interconnect transceivers to a each other or a bus. see figures 20 and 21. a NB3N200Sdg, nb3n202sdg, nb3n204sdg, and nb3n205sdg can be used as the driver or as a receiver.
NB3N200S http://onsemi.com 16 figure 20. multidrop or distributed simplex with single termination figure 21. multidrop or distributed simplex with double termination half duplex multinode multipoint theory configurations : data flow is unidirectional and selected from one of multiple possible drivers to multiple receives. one ?two node? multipoint connection can be accomplished with a single evaluation board. more than two nodes requires multiple evaluation test boards. parallel terminated interconnects yield typical mlvds amplitude levels and minimizes reflections. parallel terminated interconnects yield typical lmvds amplitude levels and minimizes reflections. on the test board, headers p1, p2, and p3 may be used as need to interconnect transceivers to each other or a bus. see figure 22. a nb3n202sdg, nb3n204sdg, and nb3n205sdg can be used as the driver or as a receiver. full duplex bus interconnect configurations are possibe using nb3n202sdg or nb3n205sdg. figure 22. multinode multipoint half duplex (requires double termination) figure 23.
NB3N200S http://onsemi.com 17 ordering information device receiver pin 1 quadrant package shipping ? NB3N200Sdg type 1 q1 soic 8 (pb ? free) 98 units / rail NB3N200Sdr2g type 1 q1 soic 8 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NB3N200S http://onsemi.com 18 package dimensions soic ? 8 nb case 751 ? 07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NB3N200S/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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